Method for releasing stress during semiconductor devicefabrication

ABSTRACT

A semiconductor device and a method for releasing stress exerted while fabricating the semiconductor device. The method for releasing the stress, includes forming a stack layer deposited on a semiconductor sequentially with a gate oxide layer, a poly-silicon layer, a tungsten layer, and a hard mask; selectively oxidizing, wherein only the poly-silicon layer of the stack layer is oxidized; heat treating for releasing stress exerted during the selective oxidation process; and forming a gate sealing nitride layer on the stack layer heat-treated.

FIELD OF THE INVENTION

[0001] The present invention relates to semiconductor devicefabrication; and, more particularly, to a method for fabricating asemiconductor device having a gate electrode with a tungsten layer.

DESCRIPTION OF RELATED ARTS

[0002] Stacked gate structures with a poly-silicon layer, a tungsten (W)layer and a tungsten nitride (WN) layer are used to reduce resistance ofgate electrodes.

[0003] However, the stacked gate structure mentioned above has somedrawbacks such as an interfacial reaction of the poly-silicon layer, thetungsten layer and the tungsten nitride layer during a re-oxidizationprocess using H₂O or O₂, an abrupt volume expansion by an oxidation ofthe tungsten layer, and particle generation. Herein, the re-oxidizationprocess of the tungsten nitride layer is carried out to recover amicro-trench created on a gate oxide layer during an etching process anda loss generated thereby, oxidize the remnant poly-silicon layerremaining on a silicon substrate, and improve reliability of thesemiconductor device by increasing thickness of the gate oxide layerformed on an edge area of the gate electrode.

[0004] The thickness and quality of the gate oxide layer are factorsaffecting a hot carrier property, a sub-threshold voltage property suchas a leakage current property and a gate induced drain leakage (GIDL)property, a punch-through property and device operating speed.

[0005] Therefore, the re-oxidization process is an essential requisiteof semiconductor device fabrication.

[0006] To overcome the aforementioned drawbacks, a selective oxidationprocess is suggested. The selective oxidation process oxidizes only thepoly-silicon layer and the silicon substrate without oxidizing thetungsten layer and the tungsten nitride layer in a H₂ rich ambientincluding H₂O.

[0007] In short, the selective oxidation process is used for forming agate bird's beak required for obtaining superior GILD property.

[0008]FIG. 1A is a flowchart showing a method for fabricating asemiconductor device including the gate electrode having a tungstenlayer in accordance with the prior art. FIG. 1B is a cross-sectionaldiagram showing the semiconductor device according to a series of theprocesses shown in FIG. 1A.

[0009] As shown in FIG. 1A, the prior art related to semiconductordevice fabrication comprises the following processes: a gate electrodepatterning process S1 for forming a stacked gate electrode depositedsequentially with the poly-silicon layer, the tungsten nitride layer andthe tungsten layer; the selective oxidation process S2 adopting a rapidthermal process (RTP); a gate sealing nitride layer deposition processS3; a gate spacer oxide layer deposition process S4; an inter layerdielectric layer deposition process S5 usingboro-phosphor-silicate-glass (BPSG); a RTP for activating source/drainregions S6; and a heat treatment process S7 for performing the interlayer dielectric layer flow process.

[0010] Referring to FIG. 1B, a gate oxide layer 12 is grown on asemiconductor substrate 11 on which a field oxide layer (FOX) is formed.Next, the poly-silicon layer 13, the tungsten nitride layer 14, thetungsten layer 15, and a hard mask 16 are sequentially deposited on thegate oxide layer 12. Next, the hard mask 16, the tungsten layer 15, thetungsten nitride layer 14 and the poly-silicon layer 13 are etchedsequentially in order to predetermine the gate electrode.

[0011] As a next step, the selective oxidation process is carried out ina H₂O ambient for the purpose of forming the gate bird's beak. At thistime, a silicon oxide layer 18A is formed on both lateral sides of thepoly-silicon layer 13 by carrying out the selective oxidation process,and a silicon oxide layer 18B is also formed on the semiconductorsubstrate 11.

[0012] Next, the above structure including the gate electrode is coveredwith the gate sealing nitride layer 19 to prevent an oxidation of thetungsten layer 15 while proceeding a heat treatment process.

[0013] However, the semiconductor device fabricated in accordance withthe prior art has a drawback such as a deterioration of a data retentiontime property. In short, a trap or a defect is generated at a cellconjunction due to a thermal stress developed by an abrupt change inthermal history created on a wafer especially during the RTP process,and the trap or defect acts as a path for a leakage current.Accordingly, the data retention time property is deteriorated, andconsequently, a refresh time fail is induced.

[0014] As shown in FIG. 1B, for a DRAM semiconductor device having atriple stack layer constituted with the poly-silicon layer, the tungstennitride layer, and tungsten layer, the selective oxidation processshould be carried out to obtain the GILD property. At this time, theselective oxidation process uses a method that adopts the RTP processhaving a rising and falling thermal history. Accordingly, thesemiconductor substrate is affected by a stress exerted by the RTPprocess. For instance, a trap site or a defect is created at a gatechannel or a cell conjunction, and eventually, increasing a conjunctionleakage.

[0015] Now, in a 0.13 μm and less than 0.13 μm semiconductor technology,the gate sealing nitride deposition process for protecting the tungstenlayer and follow-up processes are carried out without releasing thestress occurring after the selective oxidation process is performed.Therefore, the stress becomes more serious and accordingly, adeterioration of a refresh time is manifested more frequently.

[0016]FIG. 2 is a graph showing a stress history measured while a seriesof processes in accordance with the prior art are performed. Herein, anabscissa shows each name of the processes and an ordinate shows a stresslevel measured during each of the processes. In addition, the graphshows thermal stress values measured at a gate edge, a spacer edge, atop corner of a shallow trench isolation STI or FOX top corner, and ashallow trench isolation STI or FOX, and a bottom corner of the STI orFOX.

[0017] As shown in FIG. 2, it is evident that the stress becomes moreserious during a gate oxide layer formation process, a gate electrodepatterning process and the selective oxidation process than the stressexerted during a trench formation process for forming the STI and a wellannealing process. However, the stress starts being released during aninter layer dielectric layer (ILD1) flow process. Especially, it isobserved that a strong stress is exerted during the selective oxidationprocess (X).

[0018] Accordingly, a special method for technically releasing thestress exerted during the selective oxidation process is required.

SUMMARY OF THE INVENTION

[0019] It is, therefore, an object of the present invention to provide amethod for releasing stress exerted during a semiconductor devicefabricating process.

[0020] In accordance with an aspect of the present invention, there isprovided the method for releasing the stress, including: forming a stacklayer deposited on a semiconductor sequentially with a gate oxide layer,a poly-silicon layer, a tungsten layer, and a hard mask; carrying out aselective oxidation process, wherein the poly-silicon layer of the stacklayer is only oxidized; performing a heat treatment process forreleasing a stress exerted during the selective oxidation process; andcarrying out a process for forming a gate sealing nitride layer on thestack layer heat-treated.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Other objects and aspects of the invention will become apparentfrom the following description of the embodiments with reference to theaccompanying drawings, in which:

[0022]FIG. 1A is a flowchart illustrating a method for fabricating asemiconductor device including a gate electrode with a tungsten layer inaccordance with the prior art;

[0023]FIG. 1B is a cross-sectional view of the semiconductor devicefabricated in accordance with the method illustrated in FIG. 1A;

[0024]FIG. 2 is a diagram showing a history of the stress exerted as aseries of processes are carried out in accordance with a prior art;

[0025]FIG. 3 is a flowchart showing a method for fabricating asemiconductor device in accordance with a first preferred embodiment ofthe present invention;

[0026]FIG. 4 is a flowchart showing a method for fabricating asemiconductor device in accordance with a second preferred embodiment ofthe present invention;

[0027]FIG. 5 is a diagram showing a thermal history tendency of a seriesof deposition processes for a gate sealing nitride layer shown in FIG. 3and FIG. 4;

[0028]FIG. 6 is a diagram showing a flowchart of a method forfabricating a semiconductor device in accordance with a third preferredembodiment of the present invention; and

[0029]FIG. 7 is a graph showing a stress change before and after a heattreatment process.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] Hereinafter, a method is disclosed for releasing stress exertedduring fabrication of a semiconductor device including a gate electrodewith a tungsten layer.

[0031]FIG. 3 is a flowchart showing a method for fabricating asemiconductor device in accordance with a first preferred embodiment ofthe present invention.

[0032] Referring to FIG. 3, the semiconductor device in accordance withthe first preferred embodiment of the present invention is fabricatedthrough the following sequential process steps: a gate electrodepatterning process S11 forming a gate electrode stacked sequentiallywith a poly-silicon layer, a tungsten nitride layer and a tungstenlayer; a selective oxidation process S12 adopting a rapid thermalprocess (RTP); a vacuum heat treatment process S13 using a low pressurechemical vapor deposition (LPCVD) furnace; a gate sealing nitride layerdeposition process S14; a gate spacer oxide layer deposition processS15; an inter layer dielectric layer (ILD1) deposition process S16 usinga boro-phospho-silicate-glass (BPSG); another RTP for activatingsource/drain regions S17; and a heat treatment process S18 for the interlayer dielectric layer (ILD1) flow. Herein, both the vacuum heattreatment process S13 and the gate sealing nitride layer depositionprocess S14 using the LPCVD furnace are carried out under an in-situmethod.

[0033] As shown in FIG. 3, the vacuum heat treatment process S13 usingthe LPCVD furnace is carried out right after the selective oxidationprocess S12 adopting the rapid thermal process. Herein, the vacuum heattreatment is used for not only removing a trap or defect generated at acell conjunction of a semiconductor substrate but also releasing stresscaused by the RTP process used during the selective oxidation processS12, wherein the cell conjunction is formed at a bottom of the gateoxide layer.

[0034] As a next step, the gate sealing nitride layer deposition processS14 is performed to prevent the tungsten layer from being oxidizedabnormally during succeeding processes. At this time, the gate sealingnitride layer is deposited under the in-situ method by using the LPCVDfurnace. More specifically, the gate sealing nitride layer is depositedunder the in-situ method after gradually decreasing a heat treatmenttemperature to a target temperature during the vacuum heat treatmentprocess S13 using the LPCVD furnace.

[0035] Eventually, since both of the vacuum heat treatment process S13and the gate sealing nitride layer deposition process S14 using theLPCVD furnace are carried out under the in-situ method, the trap ordefect generated by the stress induced during the selective oxidationprocess S12 can be cured and thereby, the leakage path of the cellconjunction is removed by recovering a distorted semiconductorsubstrate. Herein a temperature of the LPCVD furnace is increased aboveabout 750° C. at a slowly rising rate and decreased thereafter in orderto recover the distorted semiconductor substrate.

[0036] In addition, the vacuum heat treatment process S13 using theLPCVD furnace is performed at a high temperature and at a normalpressure in a nitrogen gas ambient for a predetermined time.Accordingly, a series of the processes mentioned above impedesimpurities from existing in the nitrogen gas and the tungsten layer fromabnormally being oxidized at a normal pressure. Furthermore, it ispossible to obtain a simplified process for fabricating thesemiconductor device by using the in-situ vacuum heat treatment methodduring the gate sealing nitride layer deposition.

[0037] The in-situ method of the heat treatment process and the gatesealing nitride layer deposition process will now be described morespecifically. First of all, the semiconductor substrate to which theselective oxidation process is implemented is loaded into the LPCVDfurnace and heat-treated by increasing the temperature of the LPCVDfurnace from normal room temperature to a target temperature in vacuumambient. Next, the gate sealing nitride layer is deposited while thetemperature of the LPCVD furnace is decreased from the heat treatmenttemperature to a deposition temperature for depositing the gate sealingnitride layer. As a last step, the temperature of the LPCVD furnace isdecreased to the normal temperature and the semiconductor device isunloaded from the LPCVD furnace. Herein, the heat treatment temperatureranges from about 750° C. to about 1000° C. and the vacuum ambient has apressure of about 10⁻³ torr to about 10−2 torr. Preferably, the risingrate of the temperature for the heat treatment process ranges from about3° C./min to about 25° C./min and a falling rate of the temperatureduring the gate sealing nitride layer deposition ranges from 3° C./minto about 25° C./min. Also, the total heat treatment time is within arange of about 10 minutes to about 240 minutes.

[0038]FIG. 4 is a flow chart showing a method for fabricating asemiconductor device in accordance with a second preferred embodiment ofthe present invention.

[0039] Referring to FIG. 4, the semiconductor device in accordance withthe second preferred embodiment of the present invention is fabricatedthrough the following sequential processes: a gate electrode patterningprocess S21 forming a stacked gate electrode stacked sequentially with apoly-silicon layer, a tungsten nitride layer, and a tungsten layer; aselective oxidation process S22 adopting a RTP; a vacuum heat treatmentprocess S23 using a low pressure chemical vapor deposition (LPCVD)furnace; a gate sealing nitride layer deposition process S24 using theLPCVD furnace; a gate spacer oxide layer deposition process S25; an ILD1deposition process using BPSG S26; a RTP for activating source/drainregions S27; and a heat treatment process for the ILD1 flow S28. Herein,the vacuum heat treatment process S23 and the gate sealing nitride layerdeposition process S22 both using the LPCVD furnace are carried outunder an ex-situ method.

[0040] As shown in FIG. 4, the vacuum heat treatment process S23 usingthe LPCVD furnace is carried out right after the selective oxidationprocess S22 adopting the RTP. Herein, the vacuum heat treatment processS23 is for not only curing a trap or defect generated at a cellconjunction of a semiconductor substrate formed at a bottom of the gateoxide layer but also releasing a stress caused by the RTP used duringthe selective oxidation process S22.

[0041] As a next step, the gate sealing nitride layer deposition processS24 is performed in the same LPCVD furnace or two different LPCVDfurnaces under the ex-situ method so as to prevent the tungsten layerfrom being oxidized abnormally during succeeding processes.

[0042] More specifically, the semiconductor substrate at which theselective oxidation process has been performed is loaded in a firstLPCVD furnace. Herein, a temperature of the first LPCVD furnace isslowly increased and the semiconductor substrate is heat-treated in avacuum ambient. Next, the temperature of the first LPCVD furnace isdecreased to a room temperature and the semiconductor substrate isunloaded from the first LPCVD furnace. As a next step, the unloadedsemiconductor substrate is loaded again into the first LPCVD furnace ora second LPCVD furnace, wherein a gate sealing nitride layer isdeposited on the semiconductor substrate. At this time, the heattreatment temperature ranges from about 750° C. to about 1000° C., andthe vacuum ambient has a pressure of about 10⁻³ torr to about 10⁻² torr.Preferably, the rising rate of the heat treatment temperature is fromabout 3° C./min to about 25° C./min, the falling rate of the depositiontemperature ranges from about 1° C./min to about 20° C./min. Also, thetotal heat treatment time is from about 10 mins to about 240 mins.

[0043]FIG. 5 is a diagram showing a thermal history tendency of thedeposition processes for the gate sealing nitride layer shown in FIG. 3and FIG. 4.

[0044] Referring to FIG. 5, the semiconductor substrate is loaded intothe LPCVD furnace and then is heat-treated through gradually increasinga temperature of the LPCVD furnace. The temperature of the LPCVD isdecreased after finishing the heat treatment and the gate sealingnitride layer is deposited thereafter. As a last step, the temperatureof the LPCVD furnace is decreased to room temperature at which thesemiconductor substrate was loaded and the semiconductor substrate isunloaded from the LPCVD furnace. At this time, an ambient in the LPCVDfurnace is kept in a vacuum condition until depositing the gate sealingnitride layer.

[0045]FIG. 6 is a flow chart showing a method for fabricating asemiconductor device in accordance with a third preferred embodiment ofthe present invention.

[0046] Referring to FIG. 6, the semiconductor device in accordance withthe third preferred embodiment of the present invention is fabricatedthrough the following sequential processes: a gate electrode patterningprocess S31 forming a stacked gate electrode stacked sequentially with apoly-silicon layer, a tungsten nitride layer, and a tungsten layer; aselective oxidation process adopting a RTP S32; a gate sealing nitridelayer deposition process S33; a heat treatment process S34 using a lowpressure chemical vapor deposition (LPCVD) furnace or an annealingfurnace; a gate spacer oxide layer deposition process S35; an interlayer dielectric layer(ILD1) deposition process S36 using the BPSGmaterial; a RTP for activating source/drain regions S37; and a heattreatment process for the ILD1 flow.

[0047] As shown in FIG. 6, compared with the first and second preferredembodiments, the heat treatment process S34 according to the thirdpreferred embodiment is carried out in the LPCVD furnace or theannealing furnace in order to release a stress exerted after finishingthe gate sealing nitride layer deposition process. Furthermore, the heattreatment process mentioned above releases not only the stress exertedduring the selective oxidation process S32 but also the stress exertedduring the gate sealing nitride layer deposition process S33.

[0048] More specifically, the heat treatment process is carried out inthe LPCVD furnace or the annealing furnace in a vacuum ambient or in anitrogen or inert gas ambient. At this time, a temperature for the heattreatment is gradually increased over about 750° C. and is slowlydecreased to room temperature after finishing the heat treatment. Inaddition, the gate sealing nitride deposition process (S33) and the heattreatment process S34 are carried out in two same types of furnaces ortwo different types of furnaces under an ex-situ method.

[0049] In particular, there are two ex-situ methods used for the gatesealing nitride layer deposition process S33 and the heat treatmentprocess S34. Explaining the first ex-situ method in detail, in a firstLPCVD furnace, the gate sealing nitride layer is deposited and thesemiconductor substrate deposited with the gate sealing nitride layer isloaded in a second LPCVD furnace. Next, a temperature of the secondLPCVD furnace is gradually increased from room temperature to a targetheat treatment temperature and the semiconductor substrate isheat-treated in a vacuum ambient. After finishing the heat treatmentprocess, the temperature of the second LPCVD furnace is decreased fromthe target heat treatment temperature to room temperature and thesemiconductor substrate is unloaded thereafter. Explaining the secondex-situ method, the gate sealing nitride layer is deposited on thesemiconductor substrate in the LPCVD furnace and then, the semiconductorsubstrate is loaded in the annealing furnace. Next, a temperature of theannealing furnace is slowly increased from room temperature to a targetheat treatment temperature, and the semiconductor substrate isheat-treated in a vacuum ambient. Continuously, the heat treatmenttemperature is decreased to room temperature and the semiconductorsubstrate is unloaded thereafter.

[0050] During the heat treatment processes in accordance with the firstex-situ method and the second ex-situ method, the heat treatmenttemperature for the heat treatment process ranges from about 750° C. toabout 1000° C. and the vacuum ambient has a pressure of about 10⁻³ torrto about 10⁻² torr. Particularly, a rising rate of the heat treatmenttemperature ranges from about 3° C./min to about 25° C./min, and afalling rate of the temperature until the semiconductor substrate isunloaded ranges from about 1° C./min to about 20° C./min. Also, a totalheat treatment time ranges from about 10 minutes to about 240 minutes.

[0051]FIG. 7 is a graph showing changes in the stress before and after aheat treatment process. An ordinate expresses the stress in a numericalvalue and an abscissa shows each area at which each numerical value ofthe stress is measured. Concretely, the stress is measured at a gateelectrode edge, a spacer edge, a top corner of a shallow trenchisolation (STI or FOX) and a bottom corner of the STI.

[0052] As shown in FIG. 7, compared with a base case in which there isno heat treatment process for releasing the stress exerted after theselective oxidation process, a case of the heat treatment performedbefore depositing the gate sealing nitride layer, another case of theheat treatment performed after depositing the same, and another case ofthe heat treatment performed before and after depositing the same showthat the stress values measured at each area are generally decreased.

[0053] Table. 1 shows a comparison of a refresh time (tREF) value of thesemiconductor device fabricated in accordance with the prior art withthe tREF value of the semiconductor device fabricated in accordance withthe present invention TABLE 1 Applied art Improved portion/250 ms (tREF)Prior art 89.2 ms/250 ms Vacuum heat treatment-30 secs 91.3 ms/250 ms(Present Invention) Vacuum heat treatment-60 secs 92.1 ms/250 ms(Present Invention)

[0054] According to Table. 1, it is confirmed that the refresh time isimproved when the vacuum heat treatment process is used. Furthermore, itis also shown that the refresh time is improved as the vacuum heattreatment process time is increased.

[0055] While the present invention has been shown and described withrespect to the particular embodiments, it will be apparent to thoseskilled in the art that many changes and modification may be madewithout departing from the spirit and scope of the invention as definedin the appended claims.

What is claimed is:
 1. A method for fabricating a semiconductor device,comprising the steps of: a) forming a stack layer of a gate layer, apoly-silicon layer, a tungsten layer, and a hard mask sequentiallydeposited on a semiconductor substrate; b) selectively oxidizing onlythe poly-silicon layer of the stack layer; c) heat treating the stacklayer to release stress exerted during the selective oxidizing; and d)forming a gate sealing nitride layer on the heat treated stack layer. 2.The method as recited in claim 1, wherein the heat treating and the gatesealing nitride layer forming are carried out using a low pressurechemical vapor deposition (LPCVD) furnace under an in-situ method. 3.The method as recited in claim 2, wherein the in-situ method includesthe steps of: a1) loading the semiconductor substrate at which theselective oxidizing is carried out in the LPCVD furnace; b1) wherein theheat treating increases a temperature of the LPCVD furnace from roomtemperature to a target temperature and keeps the target temperature ina vacuum ambient; c1) depositing the gate sealing nitride layer afterdecreasing the temperature of the LPCVD furnace from the targettemperature for the heat treating to a target temperature for depositingthe gate sealing nitride layer; and d1) unloading the semiconductorsubstrate after decreasing the temperature of the LPCVD furnace to roomtemperature.
 4. The method as recited in claim 3, wherein the targettemperature for the heat treating ranges from about 750° C. to about1000° C. and a pressure of the vacuum ambient ranges from about 10 ⁻³torr to about 10⁻² torr.
 5. The method as recited in claim 3, wherein arising rate of the temperature for the heat treating ranges from about3° C./min to about 25° C./min.
 6. The method as recited in claim 3,wherein a falling rate of the temperature for depositing the gatesealing nitride layer ranges from about 1° C./min to about 20° C./min.7. The method as recited in claim 3, wherein the heat treating iscarried out for about 10 minutes to about 240 minutes.
 8. The method asrecited in claim 1, wherein the heat treating and the gate sealingnitride layer forming are carried out in two different LPCVD furnacesunder an ex-situ method.
 9. The method as recited in claim 8, whereinthe ex-situ method includes the steps of: a2) loading the semiconductorsubstrate at which the selective oxidizing is carried out in a first lowpressure chemical vapor deposition (LPCVD) furnace; b2) performing theheat treating by increasing a temperature of the first LPCVD furnacefrom room temperature to a target and keeping the target temperature ina vacuum ambient; c2) unloading the semiconductor substrate afterdecreasing the temperature of the first LPCVD furnace to roomtemperature; and d2) depositing the gate sealing nitride layer aftermoving the unloaded semiconductor substrate in the first LPCVD furnaceto the second LPCVD furnace. 10 The method as recited in claim 9,wherein the target temperature for the heat treating ranges from about750° C. to about 1000° C. and a pressure of the vacuum ambient rangesfrom about 10⁻³ torr to about 10⁻² torr.
 11. The method as recited inclaim 9, wherein a rising rate of the temperature for the heat treatingranges from about 3° C./min to about 25° C./min.
 12. The method asrecited in claim 9, wherein a falling rate of the temperature fordepositing the gate sealing nitride layer ranges from about 1° C./min toabout 20° C./min.
 13. The method as recited in claim 9, wherein the heattreating is carried out for about 10 minutes to about 240 minutes.
 14. Amethod for fabricating a semiconductor device, comprising the steps of:a3) forming a stack layer of a gate oxide layer, a poly-silicon layer, atungsten layer, and a hard mask sequentially deposited on asemiconductor substrate; b3) selectively oxidizing only the poly-siliconlayer of the stack layer; c3) depositing a gate sealing nitride layer onthe selectively oxidized stack layer; and d3) heat treating the stacklayer to release stress exerted during the selective oxidizing and gatesealing nitride layer depositing.
 15. The method as recited in claim 14,wherein the selective oxidizing and the heat treating are carried out intwo different LPCVD furnaces under an ex-situ method.
 16. The method asrecited in claim 15, wherein the ex-situ method includes the steps of:a4) depositing the gate sealing nitride layer on the semiconductorsubstrate in a first low pressure chemical vapor deposition (LPCVD)furnace; b4) loading the semiconductor substrate on which the gatesealing nitride layer is deposited in a second LPCVD furnace; c4)performing the heat treating by increasing a temperature of the secondLPCVD furnace from room temperature to a target temperature andmaintaining the target temperature in a vacuum or inert gas ambient; andc5) unloading the semiconductor substrate after decreasing thetemperature of the second LPCVD furnace from the target temperature toroom temperature.
 17. The method as recited in claim 15, wherein theex-situ method includes the steps of: a6) depositing the gate sealingnitride layer in the LPCVD furnace; b6) loading the semiconductorsubstrate on which the gate sealing nitride layer is deposited in anannealing furnace used for the heat treating; c6) carrying out the heattreating by increasing a temperature of the annealing furnace from roomtemperature to a target temperature and maintaining the targettemperature in a vacuum or inert gas ambient; and d6) unloading thesemiconductor substrate after decreasing the temperature of theannealing furnace.
 18. The method as recited in claim 16, wherein thetemperature for the heat treating ranges from about 750° C. to about1000° C. and a pressure of the vacuum ambient ranges from about 10⁻³torr to about 10⁻² torr.
 19. The method as recited in claim 16, whereina rising rate of the temperature for the heat treating ranges from about3° C./min to about 25° C./min.
 20. The method as recited in claim 16,wherein a falling rate of the temperature for the heat treating rangesfrom about 1° C./min to about 20° C./min
 21. The method as recited inclaim 17, wherein the temperature for the heat treating ranges fromabout 750° C. to about 1000° C. and a pressure of the vacuum ambientranges from about 10⁻³ torr to about 10⁻² torr.
 22. The method asrecited in claim 17, wherein a rising rate of the temperature for theheat treating ranges from about 3° C./min to about 25° C./min.
 23. Themethod as recited in claim 16, wherein a falling rate of the temperaturefor the heat treating ranges from about 1° C./min to about 20° C./min.